In the context of this disclosure, Circuit-Under-Pad, or CUP, refers to semiconductor device topologies in which large area metal contact pads are provided over areas of underlying active devices or active integrated circuitry. The large area metal pads are defined by one or more on-chip conductive metallization layers and provide for die-to-package interconnections which are distributed over the active device area. The large area metal pads are vertically interconnected to the underlying regions of the active circuitry, e.g. using a plurality of micro-vias. In contrast, in traditional, non-CUP, device topologies, on-chip metal interconnect, comprising conductive tracks, laterally interconnects active device areas to busses placed between active device areas, and external contact pads to the buses are provided, typically around the periphery of the chip. However, in the latter structures, the metal interconnect buses and contact pads are provided on inactive regions of the chip, which take up significant area in between active device regions and/or around edges of the die, limiting the usable fraction of the die area that is available for the active device area.
CUP device structures are effective in increasing the usable fraction of die area available for active circuitry, and potentially provide for physical and electrical shielding of underlying circuitry, and more planar encapsulation. On the other hand, for application to power switching devices, such as high-current lateral GaN transistors, known implementations of CUP device topologies have one or more limitations, such as, limited current carrying capability. Other important considerations for high current power switching devices include reducing on-chip parasitic capacitances and inductances, e.g. source-drain capacitance and gate loop inductance. Improvements are needed to address these issues.
Improved or alternative device topologies and packaging solutions for high current, lateral GaN transistors are disclosed, for example, in the Applicant's above-referenced related co-pending U.S. patent application Ser. No. 15/704,458, entitled “High Current Lateral GaN Transistors with Scalable Topology and Gate Drive Phase Equalization”, of which this application is a continuation-in-part, and references cited therein. For example, large area, lateral GaN transistors for high voltage/high current operation, such as GaN power switches comprising GaN E-HEMTs, may comprise a plurality of transistor elements connected in parallel. In one embodiment, the device topology of a large area, large gate width GaN E-HEMT may comprise a plurality of transistor elements in the form of islands. Each island comprises individual source, drain and gate finger electrodes and a plurality of islands are interconnected to form a multi-island transistor. The “islands” may alternatively be referred to as cells or sections of a multi-cell or multi-section transistor. An overlying conductive interconnect structure is provided which comprises a source bus, a drain bus and a gate bus which interconnect respective source, drain and gate electrodes of each island.
By way of example, other device topologies and packaging solutions for lateral GaN transistors are disclosed in the following patent documents:
U.S. patent application Ser. No. 14/568,507, filed Dec. 12, 2014, now U.S. Pat. No. 9,153,509 entitled “Fault Tolerant Design for Large Area Nitride Semiconductor Devices”;
U.S. patent application Ser. No. 15/091,867, filed Apr. 6, 2016, now U.S. Pat. No. 9,660,639, entitled “Distributed Driver Circuitry integrated with GaN Power Transistors”;
U.S. patent application Ser. No. 15/091,867, filed Apr. 6, 2016, now U.S. Pat. No. 9,660,639, entitled “Distributed Driver Circuitry integrated with GaN Power Transistors”;
U.S. patent application Ser. No. 15/027,012, filed Apr. 15, 2015, now U.S. Pat. No. 9,659,854, entitled “Embedded Packaging for Devices and Systems Comprising Lateral GaN Power Transistors”;
U.S. patent application Ser. No. 15/064,750, filed Mar. 9, 2016, now U.S. Pat. No. 9,589,868, entitled “Packaging Solutions for Devices and Systems Comprising Lateral GaN Power Transistors”;
U.S. patent application Ser. No. 15/064,955, filed Mar. 9, 2016, now U.S. Pat. No. 9,589,869, entitled “Packaging Solutions for Devices and Systems Comprising Lateral GaN Power Transistors”;
U.S. patent application Ser. No. 14/681,676, filed Apr. 8, 2015, now U.S. Pat. No. 9,508,797, entitled “Gallium Nitride Power Devices using Island Topography”;
U.S. patent application Ser. No. 1/020,712, filed Feb. 3, 2011, now U.S. Pat. No. 9,029,866, entitled “Gallium Nitride Power Devices using Island Topography”;
U.S. patent application Ser. No. 13/641,003, filed Apr. 13, 2011, now U.S. Pat. No. 8,791,508 entitled “High Density Gallium Nitride Devices using Island Topology”; and
U.S. patent application Ser. No. 13/388,694, filed Aug. 4, 2010, now U.S. Pat. No. 9,064,947 entitled “Island Matrixed Gallium Nitride Microwave and Power Switching Transistors”.
All the above referenced patents and patent applications are incorporated herein by reference in their entirety.
There is a need for improved or alternative CUP device topologies for high current, power switching devices, which mitigate or circumvent limitations of known CUP device topologies, particularly for application to power switching systems comprising high current lateral GaN power transistors.